? semiconductor components industries, llc, 2011 january, 2011 ? rev. 4 1 publication order number: ntmke4890n/d ntmke4890n power mosfet 30 v, 155 a, single n ? channel, icepak features ? low package inductance ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? dual sided cooling capability ? compatible with mx footprint and outline ? these are pb ? free devices applications ? cpu power delivery ? dc ? dc converters ? optimized for both synch fet maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 32 a t a = 70 c 25.5 power dissipation r ja (note 1) t a = 25 c p d 2.8 w continuous drain current r j ? pcb (note 2) t a = 25 c i d 155 a t a = 70 c 86 power dissipation r j ? pcb (note 2) t a = 25 c p d 65 w continuous drain current r jc (note 1) t c = 25 c i d 192 a t c = 70 c 154 power dissipation r jc (note 1) t c = 25 c p d 100 w pulsed drain current t a = 25 c, t p = 10 s i dm 244 a current limited by package t a = 25 c i dmax 50 a operating junction and storage temperature t j , t stg ? 40 to 150 c source current (body diode) (note 1) i s 128 a drain to source dv/dt dv/dt 6.0 v/ns single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = 30 v, v gs = 10 v, i l = 58 a pk , l = 0.3 mh, r g = 25 ) e as 505 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 270 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surfacemounted on fr4 board using 1 sq ? in pad, 1 oz cu. 2. measured with a t j of approximately 90 c using 1 oz cu board. 3. surfacemounted on fr4 board using 1 sq ? in pad, 2 oz cu. http://onsemi.com device package shipping ? ordering information v (br)dss r ds(on) max i d max 30 v 1.8 m @ 10 v 155 a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 2.5 m @ 4.5 v ntmke4890nt1g icepak (pb ? free) 1500/tape & reel NTMKE4890NT3G icepak (pb ? free) 5000/tape & reel marking diagram e4890 ayww icepak e pad case 145ab e4890= specific device code a = assembly location y = year ww = work week = pb ? free package (note: microdot may be in either location) n ? channel mosfet d
ntmke4890n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) (note 1) r jc 1.25 c/w junction ? to ? ambient ? steady state (note 1) r ja 45 junction ? to ? ambient ? steady state (notes 2 and 3) r ja 25 junction ? to ? pcb (note 2) r j ? pcb 1.0 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 20 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.4 2.4 v negative threshold temperature coefficient v gs(th) /t j 5.9 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 30 a 1.5 1.8 m v gs = 4.5 v, i d = 30 a 2.1 2.5 forward transconductance g fs v ds = 15 v, i d = 25 a 120 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 15 v 7100 pf output capacitance c oss 1360 reverse transfer capacitance c rss 690 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 25 a 51.7 nc threshold gate charge q g(th) 6.0 gate ? to ? source charge q gs 18.8 gate ? to ? drain charge q gd 18.6 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 25 a 104 nc switching characteristics (note 5) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 25 a, r g = 2.0 25 ns rise time t r 23 turn ? off delay time t d(off) 42 fall time t f 12 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 20 a t j = 25 c 0.78 1.0 v t j = 125 c 0.68 reverse recovery time t rr v gs = 0 v, d is /d t = 200 a/ s, i s = 20 a 41.8 ns charge time t a 19.4 discharge time t b 22.4 reverse recovery charge q rr 61 nc package parasitic values gate resistance r g t a = 25 c 0.6 1.5 4. pulse test: pulse width = 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures.
ntmke4890n http://onsemi.com 3 typical characteristics 4.0 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 20 40 60 80 160 180 200 4 3 2 0 20 40 160 i d , drain current (a) i d , drain current (a) 100 120 140 t j = 25 c 10 v 7.0 v 3.8 v 3.6 v 3.4 v 3.2 v 3.0 v 2.6 v v ds 10 v t j = 25 c t j = 125 c t j = ? 55 c 60 80 120 140 100 4.5 3.5 2.5 1.5 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 10 9 8 7 5 4 3 0.001 0.002 0.003 0.004 0.006 0.007 130 105 80 55 30 5 0.0010 0.0014 0.0018 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.6 0.7 1.0 1.2 1.5 20 15 10 5 100 100000 r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 6 0.005 i d = 34 a t j = 25 c 205 t j = 25 c v gs = 4.5 v v gs = 10 v r ds(on) , drain ? to ? source resistance ( ) 150 i d = 29 a v gs = 10 v 30 t j = 150 c v gs = 0 v t j = 125 c 0.9 1.1 1.4 1.6 0.8 1.3 0.008 180 155 10000 2.8 v 0.0012 0.0016 0.0020 0.0022 0.0024 1000 200 180 25
ntmke4890n http://onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge gate ? to ? source or drain ? to ? source voltage (v) q g , total gate charge (nc) 25 20 15 10 0 0 2000 3000 4000 5000 6000 7000 9000 90 70 60 50 40 20 10 0 0 2 4 10 12 c, capacitance (pf) v gs , gate ? to ? source voltage (v) 1000 t j = 25 c v gs = 0 v c oss c iss c rss 30 80 8 6 i d = 27 a t j = 25 c v gs = 4.5 v qt 8000 5 110 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.8 0.7 0.5 0.9 0 5 25 figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy vs. starting junction temperature v ds , drain ? to ? source voltage (v) t j , starting junction temperature( c) 100 10 1 0.01 0.01 1 10 100 1000 75 150 125 100 50 25 0 t, time (ns) i s , source current (a) i d , drain current (a) e as , single pulse drain ? to ? source avalanche energy (mj) v dd = 15 v i d = 27 a v gs = 4.5 v t f t r t d(off) t d(on) 10 15 20 30 v gs = 0 v t j = 25 c 10 s 100 s 1 ms 10 ms dc 0 v gs 20 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 200 i d = 58 a 0.1 0.4 0.6 100 q gd q gs 45 35 40 50 0.1 300 400 500 600
ntmke4890n http://onsemi.com 5 typical characteristics figure 13. thermal impedance 0.1 0.00001 pulse time (s) 100 1 0.1 0.01 0.0001 0.001 0.01 1.0 10 100 0.000001 50% (duty cycle) 20% 10% 5.0% 2.0% 1.0% single pulse 1000 r(t) (c/w) 10
ntmke4890n http://onsemi.com 6 package dimensions icepak 6.3x4.9 ? e pad case 145ab ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to the flanges of leadframe only. seating plane d e a a2 dim a min max millimeters 0.61 0.68 a1 0.02 0.08 f 0.94 bsc a2 0.08 0.17 g 2.54 bsc d 6.25 6.35 0.35 0.45 d2 gate pad reference 0.08 c 0.08 c note 3 d3 d4 e2 2x 1.38 1.42 d3 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.75 2.35 1.75 1.85 4x 1.45 2x dimensions: millimeters top view side view bottom view f 0.68 0.72 d4 4.80 5.05 e g 0.90 0.75 1.22 e3 3.85 3.95 e2 0.80 0.84 e3 0.68 0.72 e4 0.38 0.42 h c a1 0.10 c a a 0.10 c a 0.87 2x 4x 1.75 2.90 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ntmke4890n/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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